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LTC2351-14
8
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PIN FUNCTIONS
VDD (Pin 25): 3V Positive Digital Supply. This pin sup-
plies 3V to the logic section. Bypass to DGND pin and
solid analog ground plane with a 10μF ceramic capacitor
(or 10μF tantalum in parallel with 0.1μF ceramic). Keep
in mind that internal digital output signal currents ow
through this pin. Care should be taken to place the 0.1μF
bypass capacitor as close to Pin 25 as possible. Pin 25
must be tied to Pin 24.
SEL2 (Pin 26): Most Signicant Bit Controlling the
Number of Channels Being Converted. In combination
with SEL1 and SEL0, 000 selects just the rst channel
(CH0) for conversion. Incrementing SELx selects addi-
tional channels(CH0–CH5) for conversion. 101, 110 or 111
select all six channels for conversion. Must be kept in a
xed state during conversion and during the subsequent
conversion to read data.
SEL1 (Pin 27): Middle Signicant Bit Controlling the
Number of Channels Being Converted. In combination
with SEL0 and SEL2, 000 selects just the rst channel
(CH0) for conversion. Incrementing SELx selects additional
channels for conversion. 101, 110 or 111 select all six
channels (CH0–CH5) for conversion. Must be kept in a
xed state during conversion and during the subsequent
conversion to read data.
SEL0 (Pin 28): Least Signicant Bit Controlling the
Number of Channels Being Converted. In combination
with SEL1 and SEL2, 000 selects just the rst channel
(CH0) for conversion. Incrementing SELx selects addi-
tional channels for conversion. 101, 110 or 111 select all
six channels (CH0–CH5) for conversion. Must be kept in
a xed state during conversion and during the subsequent
conversion to read data.
BIP (Pin 29): Bipolar/Unipolar Mode. The input dif-
ferential range is 0V – 2.5V when BIP is LOW, and it is
±1.25V when BIP is HIGH. Must be kept in xed state
during conversion and during subsequent conversion to
read data. When changing BIP between conversions the
full acquisition time must be allowed before starting the
next conversion. The output data is in 2’s complement
format for bipolar mode and straight binary format for
unipolar mode.
CONV (Pin 30): Convert Start. Holds the six analog input
signals and starts the conversion on the rising edge. Two
CONV pulses with SCK in xed HIGH or xed LOW state
starts nap mode. Four or more CONV pulses with SCK in
xed HIGH or xed LOW state starts sleep mode.
DGND (Pin 31): Digital Ground. This ground pin must be
tied directly to the solid ground plane. Digital input signal
currents ow through this pin.
SCK (Pin 32): External Clock Input. Advances the con-
version process and sequences the output data at SD0
(Pin1) on the rising edge. One or more SCK pulses wake
from sleep or nap power saving modes. 16 clock cycles
are needed for each of the channels that are activated by
SELx (Pins 26, 27, 28), up to a total of 96 clock cycles
needed to convert and read out all six channels.
Exposed Pad (Pin 33): GND. Must be tied directly to the
solid ground plane.
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